This invention relates, in general, to processing semiconductor devices and, more particularly, to an improved method for forming tapered contact openings in insulating layers of semiconductor devices.
It has long been known that there exists a need, in the manufacture of semiconductor devices, to round the corners of contact holes in the lower layers of a multi-layer structure so that when subsequent layers are deposited, the surface presented to the subsequently deposited layer will not have sharp or abrupt steps to traverse at the edges of the contact holes. Deposition of the subsequent layers, without the prior removal of the steep step contours may result in cracks or discontinuity in any metal interconnect line which must be deposited in the contact hole. Since a properly tapered and contoured contact hole is the key to successfully interconnecting the various elements of an integrated circuit, it is imperative that the metallization layer be crack-free in order to produce consistently operative devices. Thus, from the point of view of both high reliability and high yield, a smooth contoured contact hole is required for all integrated circuit devices and, in particular, for high density MOS devices.
An additional caveat must be observed when the high density MOS integrated circuit uses scaled MOS field effect transistors (MOSFET's). A scaled device, generally, may be defined as a MOSFET having very shallow source and drain diffusion regions, i.e., diffusion regions that are less than about 0.6 .mu.m (microns) deep and a small geometry channel length that is less than about 3.0 microns. Further, these scaled devices may also have relatively thin layers of gate oxide usually less than about 0.03 microns thick. Thus, with shallow diffusion regions, any process step that removes silicon from the diffusion region must be avoided or minimized since excessive thinning of the diffused regions will allow the metal contact to spike through the region into the underlying substrate. Additionally, because of the shallow diffusion regions, scaled MOSFET's are sensitive to precessing steps that require high temperatures since excessive heat will produce an undesirable diffusion of the ion implanted source and drain regions. Thus, since scaled devices are sensitive to the removal of silicon in the implanted regions, the use of plasma or reactive ion etching processes is severely restricted and, since they are also heat sensitive, the common reflow glasses such as the phosphosilicate family of glasses must be avoided to prevent undesired diffusion during the reflow step.